1. Field of the Invention
The present invention relates generally to output buffer circuits in semiconductor integrated circuit apparatus and, more particularly, to a reduction of an overshoot and undershoot of an output signal.
2. Description of the Background Art
A semiconductor integrated circuit apparatus in general includes an output buffer circuit. This output buffer circuit amplifies an internally generated weak signal to a predetermined level and drives externally connected load.
FIG. 14 is a block diagram showing such a semiconductor integrated circuit device. Referring to FIG. 14, the semiconductor integrated circuit device 20 includes supply terminals Vcc and Vss, a plurality of signal input terminals Si, a plurality of data output terminals DO and a semiconductor chip 21. The semiconductor chip 21 includes an output buffer circuit 22 each formed a CMOS inverter, and a data generator 23 responsive to a signal input to the signal input terminals SI for outputting data Din and an output enable signal OE. The semiconductor chip 21 is connected to respective external terminals SI, DO, Vcc and Vss by means of bonding pads 24 and bonding wires 3.
The output buffer circuit includes an input terminal Din for receiving an input signal, an output enable signal input terminal OE for receiving an output enable signal, an output terminal Dout for outputting an output signal, a power supply terminal Vcc set in a driving potential, a ground terminal GND set in a ground potential, a P channel transistor 1, an N channel transistor 2, a NOR gate 4, a NAND gate 5 and inverters 6, 7 and 8.
Input terminal Din is connected to one input terminal of NOR gate 4 and one input terminal of NAND gate 5. Output enable signal input terminal OE is connected to the other input terminal of NAND gate 5 and to the other input terminal of NOR gate 4 via inverter 6. An output terminal of NOR gate 4 is connected via inverter 7 to a gate electrode of P channel transistor 1. An output terminal of NAND gate 5 is connected via inverter 8 to a gate electrode of N channel transistor 2. P channel transistor 1 has its source electrode connected to power supply terminal Vcc and its drain electrode to a node N3. N channel transistor 1 has its source electrode connected to ground terminal GND and its drain electrode to node N3. Node N3 is connected through a bonding wire 3 to output terminal Dout. A node N1 is connected to the gate electrode of P channel transistor 1, a node N2 is connected to the gate electrode of N channel transistor 2, and a reference character "L" indicates inductance included in bonding wire 3 or the like.
In the following description, reference characters of an input signal, an output signal, an output enable signal, a supply voltage and a ground potential are provided to match those of corresponding terminals employing those corresponding signals, supply voltage and ground potential.
An operation of the output buffer device shown in FIG. 14 will now be described.
Output enable signal OE is a signal which activates the output buffer device when attaining a logic high level (hereinafter referred to as an H level) and inactivates the output buffer device when attaining a logic low level (hereinafter referred to as an L level).
When output enable signal OE is at an L level, output node N1 of inverter 7 and output node N2 of inverter 8 are at an H level and an L level, both P channel transistor 1 and N channel transistor 2 turn off, and output terminal Dout is put in a high impedance state.
If input signal Din of an H level is applied when output enable signal OE is at an H level, then an output of NOR gate 4 attains an L level, and an output of NAND gate 5 attains an L level. The output of NOR gate 4 is inverted by inverter 7, while the output of NAND gate 5 is inverted by inverter 8. Accordingly, respective output signals of respective nodes N1 and N2 attain an H level, so that N channel transistor 2 turns on and a signal of an L level is output to output terminal Dout. Similarly, when output enable signal OE and input signal Din are at an H level and an L level, respectively, both nodes N1 and N2 attain an L level, so that P channel transistor 1 turns on and an output signal of an H level is output to output terminal Dout.
In an actual semiconductor integrated circuit apparatus, there exists inductance L generated by bonding wire 3 or the like between node N3 connected in common to P channel transistor 1 and N channel transistor 2 and output Dout. Because of this inductance L, a current keeps flowing even after output signal Dout attains the ground potential or supply potential Vcc, resulting in generation of an overshoot and undershoot of the output signal.
A description will now be made on the generation of the overshoot and undershoot due to inductance L with reference to a waveform diagram of FIG. 15 and 16.
FIG. 15 (1) shows waveforms of the voltage at node N1, the voltage at the output terminal Dout and of the current flowing through the inductance L at the time of generation of an overshoot in the output buffer circuit shown in FIG. 14. FIG. 15 (2) shows energy stored in the inductance L.
FIG. 16 is a waveform diagram of simulation of input signal Din, voltages on nodes N1-N3 and output signal Dout when the output buffer device shown in FIG. 14 is rendered active. Referring to FIGS. 15 and 16, VN1 denotes a voltage waveform of node N1, VN2 denotes a voltage waveform of node N2, and VN3 denotes a voltage waveform of node N3.
An overshoot is generated in the following manner. With the logic level of input signal Din changing from an H level to an L level, the logic level of respective voltages on nodes N1 and N2 changes from an H level to an L level. P channel transistor 1 turns on from an OFF state in response to voltage VN1 on node N1, while N channel transistor 2 turns off from an ON state in response to voltage VN2 on node N2. With the transistors turning on/off, voltage VN3 on node N3 increases abruptly and a current I abruptly flows through bonding wire 3 as shown in FIG. 15 (1), so that energy is stored in inductance L as shown in FIG. 15 (2). This energy is in proportion to Ldi/dt wherein I is a current flowing through inductance L, and L is a constant of the inductance. This energy causes a current to flow even after output terminal Dout attains supply potential Vcc, whereby the overshoot is generated in the end of rising of output signal Dout.
The generation of an undershoot will now be described. With the logic level of input signal Din changing from an L level to an H level, the logic level of respective voltages VN1 and VN2 on respective nodes N1 and N2 changes from an L level to an H level. P channel transistor 1 turns off in response to the level change of voltages VN1 and VN2, so that N channel transistor 2 turns on. Consequently, voltage VN3 on node N3 falls abruptly. At this voltage fall, energy in proportion to Ldi/dt is stored in inductance L, and the stored energy still flows even after output signal Dout attains the ground potential. This results in the generation of the undershoot shown in FIG. 16.
The conventional CMOS type output buffer device in common use has a possibility that the above-described overshoot and undershoot are generated and that the overshoot and undershoot cause a spurious emission noise.
It is necessary to decrease the stored energy (Ldi/dt) in order to reduce the overshoot and undershoot; however, inductance L cannot be decreased because inductance L is attributed to bonding wire 3 or the like. Accordingly, a method of decreasing di/dt, i.e., a gradient of a current is considered. To implement this method, two methods are applied: the one is diminishing the rising or falling of voltages VN1 and VN2 on nodes N1 and N2, and the other is reducing the size of P channel transistor 1 and N channel transistor 2 and decreasing an output current to output node N3.
However, since both methods have such approach as to decrease the gradient of a current between ground potential GND and supply potential Vcc, those methods have a disadvantage that it takes longer time that output signal Dout attains supply potential Vcc or ground potential GND, and output speed is decreased.